1. Field
Exemplary embodiments of the present invention relate to a memory system including a plurality of memory devices and a memory controller for controlling the memory devices.
2. Description of the Related Art
In memory devices, such as NAND flash and Phase-Change Random Access Memory (PCRAM), the number of write operations that can be performed on a memory cell before the memory cell becomes unreliable is limited. For example, a PCRAM memory cell may have a limited number of write operations of about 106 to 108.
Accordingly, if write operations are concentrated on a specific cell region of a memory device, the service life of the memory device may be reduced substantially. To prevent such a concern, memory devices typically perform a wear leveling operation to distribute write operations more uniformly in the entire cell array of a memory device. A widely used method for wear leveling changes address mapping between a logical address and a physical address.
Many memory systems employ not only one memory device, but a plurality of memory devices. The plurality of memory devices may distribute and store data in units of pages. For example, data of one page formed of 80 bits may be distributed and stored in 5 memory devices, i.e., 16 bits per memory device. The data of a page are not changed in the same frequency, but specific data within a page may be more frequently changed. For example, if a page includes normal data and ECC data, the service life of a memory device that belongs to a plurality of memory devices and that stores the ECC data may reach the limit more quickly because the ECC data are more frequently changed than the normal data. Furthermore, normal data that is close to the Least Significant Bit (LSB) is more frequently changed than data close to the Most Significant Bit (MSB). Accordingly, the service life of a memory device that belongs to the plurality of memory devices and that stores data close to the LSB may reach the limit more quickly. That is, although the plurality of memory devices of a memory system performs the same number of write operations, the service life of a specific memory device may reach the limit more quickly.